1. Field of Invention
This invention relates to word line decoders and drivers for semiconductor memory storage systems, and more particularly to high speed, low power decoder apparatus with very small pitch compatible with the small word line pitch of a high density semiconductor memory.
2. Description of Prior Art
The present invention teaches a word line decoder and driver circuits for semiconductor memories wherein the pitch of the decoder is twice that of the word line, the number of decoders required is reduced by a half, and the word line selection pulse can be applied prior to word line selection. The prior art includes many various schemes and structures for memory decoder and driver circuits, but none having the above features embodied as in the present invention.
Representative prior art references are as follows:
U.S. Pat. No. 3,995,171 issued Nov. 30, 1976 to G. Sonoda and entitled DECODER DRIVER CIRCUIT FOR MONOLITHIC MEMORIES describes a decode circuit for word lines. A discharge path is provided for discharging the word lines to prevent false selection and improving timing.
U.S. Pat. No. 3,757,310 issued Sept. 4, 1973 to B. F. Croxon and entitled MEMORY ADDRESS SELECTION APPARATUS INCLUDING ISOLATION CIRCUITS describes an address selection structure with buffer circuits responsive to clocking signals. Each of the buffer circuits is arranged to translate low level logic address signals applied to its input terminal into a pair of high level complementary signals suitable for driving a pair of address selection lines applied to the input terminals of the decoder circuits. Prior to address selection time, a clock signal conditions the buffer to set the address line in a first state. During address selection time, a clocking signal conditions each of the buffer circuits to switch only one address selection line of each pair of lines from a first state to a second state in accordance with the state of the low level address information signal applied to its input terminal. This causes each of the decoder circuits which has one of its input terminals forced to a second state to discharge rapidly from the first predetermined state to a second predetermined state with only the addressed decoder circuits remaining at the first predetermined state.
U.S. Pat. No. 4,194,130 issued Mar. 18, 1980 to J. D. Moench and entitled DIGITAL PREDECODING SYSTEM describes an address predecoder provided in combination with an address decoder. The predecoder permits a reduction in the number of transistors used in the decoder which is preferably a MOS device NOR gate.
U.S. Pat. No. 3,909,808 issued Sept. 30, 1975 to Cochran et al and entitled MINIMUM PITCH MOSFET DECODER CIRCUIT CONFIGURATION describes a MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. The binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density. This circuit uses n-MOS technology and employs selected pass gates between the decoder and the memory.
U.S. Pat. No. 3,778,782 issued Dec. 11, 1973 to N. Kitagawa and entitled IGFET DYNAMIC ADDRESS DECODE CIRCUIT describes a high speed, low power address decode circuit which exhibits zero static power loss and increased packing density. To provide generally faster dynamic operation, the circuit precharges line and inherent capacitance prior to application of the data pulses.
U.S. Pat. No. 4,124,900 issued Nov. 7, 1978 to Smith et al, and entitled MEMORY USING INTERLEAVED ROWS TO PERMIT CLOSER SPACING describes an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
U.S. Pat. No. 3,851,186 issued Nov. 26, 1974 to J. T.-Z. Koo and entitled DECODER CIRCUIT describes a conventional MOS binary-to-one-out-of-N decoder which is modified to reduce the number of MOS devices associated with each of the N output lines of the unit. Additionally, the power consumption per output line of the modified decoder is less than that of the conventional unit.
Other prior art references in the general area of memory decoders and/or drivers includes U.S. Pat. No. 3,976,892 issued Aug. 24, 1976 to J. K. Buchanan, and entitled PRE-CONDITIONING CIRCUITS FOR MOS INTEGRATED CIRCUITS, U.S. Pat. No. 4,027,174 issued May 31, 1977 to Y. Ogata, and entitled DYNAMIC DECODER CIRCUIT, U.S. Pat. No. 4,185,320 issued Jan. 22, 1980 to Takemae et al, and entitled DECODER CIRCUIT, U.S. Pat. No. 3,786,277 issued Jan. 15, 1974 to P.-W. V. Basse and entitled CIRCUIT ARRANGEMENT OF MOS TRANSISTORS OPERATING ACCORDING TO THE DYNAMIC PRINCIPLE FOR DECODING THE ADDRESSES FOR AN MOS MEMORY, U.S. Pat. No. 4,247,921 issued Jan. 27, 1981 to Itoh et al, and entitled DECODER, U.S. Pat. No. 4,099,162 issued July 4, 1978 to P.-W. von Basse and entitled DECODER CIRCUIT, U.S. Pat. No. 4,086,500 issued Apr. 25, 1978 to Suzuki et al, and entitled ADDRESS DECODER, U.S. Pat. No. 3,641,511 issued Feb. 8, 1972 to Cricchi et al, and entitled COMPLEMENTARY MOSFET INTEGRATED CIRCUIT MEMORY, U.S. Pat. No. 4,011,549 issued Mar. 8, 1977 to A. R. Bormann, and entitled SELECT LINE HOLD DOWN CIRCUIT FOR MOS MEMORY DECODER, U.S. Pat. No. 4,074,237 issued Feb. 14, 1978 to D. P. Spampinato, and entitled WORD LINE CLAMPING CIRCUIT AND DECODER.